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WM5621L
Production Data Jan. 1997 Rev. 1.0
Low-power Quadruple 8-Bit DAC
Description
WM5621L is a quadruple 8-bit digital to analogue converter (DAC) with buffered reference inputs (high impedance). The DAC produces an output voltage that ranges between either one or two times the reference voltage and GND. The DAC is monotonic. The device operates from a single supply in the range 2.7V to 5.5V. A power-on reset function is incorporated to provide repeatable start-up conditions. A global hardware shut-down terminal and the capacity to shut-down each individual DAC with software are provided to minimize power consumption. WM5621L interfaces to all popular microcontrollers and microprocessors via a three wire serial interface with CMOS compatible, schmitt trigger, digital inputs. Alternatively a two wire serial interface can be activated. An 11-bit command word consists of eight bits of data, two DAC select bits and a range bit for selection between the times one or times two output range. The DACregisters are double buffered which allows a complete set of new values to be written to the device, and then under control of HWACT, all of the DAC outputs are simultaneously updated. Ideal in space critical applications WM5621L is available in small outline and DIP packages and is characterized for operation from -25oC to 85oC.
Features
* * * * * * * * * * * * * Individual (or all) DAC's can be powered-down One low-power 8-bit voltage output DAC Three 8-bit voltage output DACs Fast serial interface (1 MHz max) Simple 2 or 3 wire interface Programmable for 1 or 2 times output range High impedance reference inputs for each DAC Simultaneous update facility Extended temperature range (-25oC to 85 oC) Single supply operation, range 2.7 V to 5.5 V 0 to 4 V output (x2 output range) at 5 V VDD 0 to 2.5 V output (x2 output range) at 3 V VDD Low power specification: All DACs on : 3.6 mW at 3.6 V typ : 6 mW at 5 V typ Low power DAC : 0.54 mW at 3.6V typ All DAC's shutdown : 0.18 mW at 3.6V typ Guaranteed monotonic output
*
Applications
* * * * * Mobile Communications Programmable d.c. voltage sources Digitally controlled attenuator/amplifier Signal synthesis Automatic test equipment
Block Diagram
Production Data data sheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics standard terms and conditions
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK
(c) 1996 Wolfson Microelectronics
Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 email: admin@wolfson.co.uk www: http://www.wolfson.co.uk
WM5621L
Pin Configuration
Top View N or D Packages
Ordering Information
DEVICE WM5621LED WM5621LEN TEMP. RANGE -25oC to 85oC -25oC to 85oC PACKAGE 14 pin plastic SO 14 pin DIP
GND REF A REF B REF C REF D DATA CLK
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VDD HWACT DACA DACB DACC DACD EN
Absolute Maximum Ratings (note 1) Supply Voltage (VDD - GND) . . . . . . . . . . . +7V Digital Inputs . . . . . . . . . GND - 0.3 V, VDD + 0.3 V Reference inputs . . . . . . . GND - 0.3 V, VDD + 0.3 V Recommended Operating Conditions
Supply Voltage Reference input range DAC output load resistance to GND High level digital input voltage Low level digital input voltage Clock frequency Operating free-air temperature, TA
Operating temperature range, TA . . . . . -25 C to +85 C Storage Temperature . . . . . . . . . -50oC to +150 oo C Lead Temperature (soldering, 10 sec) . . . . . +260 C
o
o
MIN 2.7 GND 10 0.8 VDD
NOMINAL 3.3
MAX 5.5 VDD - 1.5
-25
0.2 VDD 1 85
UNIT V V k V V MHz O C
5
Electrical Characteristics
VDD = 3 V to 3.6V, GND = 0 V, VREF = 1.25 V, RL = 10 k, CL = 100 pF, x1 gain output range, TA = full range unless otherwise stated. PARAMETER Supply Voltage High level digital input voltage Low level digital input voltage Reference voltage, VREF [A|B|C|D] Load resistance Data input setup time Data input hold time CLK to EN EN to CLK CLK period high EN low time Clock frequency Operating free-air temperature SYMBOL CONDITIONS VDD see note 2 VIH VIL x1 gain RL tSD tHD tEN tLC cph tenl fCLK TA see note 3 see note 3 see note 3 MIN 2.7 0.8 VDD GND 10 50 50 100 100 400 200 -25 1.0 85 NOM 3.3 MAX 5.5 0.2 VDD VDD-1.5 UNIT V V V V k ns ns ns ns ns ns MHz O C
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Electrical Characteristics (continued) VDD = 3 V to 3.6V, GND = 0 V, VREF = 1.25 V, RL = 10 k, CL = 100 pF, x1 gain output range, TA = full range unless otherwise stated.
PARAMETER Max. full-scale output voltage High level input current Low level input current Output sink current DACA Output sink current DACB Output Source Current Input capacitance Reference input capacitance Supply current Supply current One low power DAC Active Supply Current ALL DACs Shutdown Reference input current Integral Nonlinearity Differential Nonlinearity Zero scale error Zero scale error temperature coefficient Zero scale error supply rejection Full scale error Full scale error temperature coefficient Full scale error supply rejection Feedback resistor network resistance Notes: 1. Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating range limits are given under Recommended Operating Conditions. Guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. 2. The device operates over the supply voltage range of 2.7V to 5.5V. Over this voltage range the device responds correctly to data input by changing the voltage output but conversion accuracy is not specified over this extended range. SYMBOL Vomax IIH IIL Io (sink) Io (sink) Io (source) CI IDD IDAC Iddsd IREF INL DNL ZCE A, B, C, D inputs VDD = 3.6V VDD = 5.0V VDD = 3.6V (Note 4) VDD = 3.6V (see note 4) A, B, C, D inputs VREF = 1.25V, Range x2. (note 5,13) VREF = 1.25V, Range x2. (note 6,13) VREF = 1.25V,Range x2. 0 (note 7) VREF = 1.25V,Input code = 00 Hex (note 8) CONDITIONS Vref=1.5V, open cct. output ,x2 gain VI = VDD VI = 0V at DAC code 0 at DAC code 0 Each DAC output, at DAC code 255 MIN VDD-100 TYP 2 MAX UNIT mV 10 10 5 20 1 15 15 1 1 150 50 A A A A mA pF pF mA mA A A A LSB LSB mV V/ OC mV/V 60 25 2 168 mV V/ C
O
1.5 1.5 250 100 10 1.0
0.1
0.9 30
10 2
FSE
Range x 2. (note 9) VREF = 1.25V,Range x2. (note 10)
mV/V k
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WM5621L
Electrical Characteristics
VDD = 3 V to 3.6V, GND = 0 V, VREF = 1.25 V, RL = 10 k, CL = 100 pF, x1 gain output range, TA = full range unless otherwise stated. PARAMETER Output slew rate rising DACA Output slew rate falling DACA Output slew rate DACB,C,D Output settling time rising DACA Output settling time falling DACA Output settling time rising DACB,C,D Output settling time falling DACB,C,D Output settling time HWACT or ACT to output volts DACA (note 14) Output settling time HWACT or ACT to output volts DACB,C,D (note 14) Large signal Bandwidth Digital crosstalk Reference feedthrough Channel-to-channel isolation Channel-to-channel isolation when in shutdown Reference bandwidth DACA Reference bandwidth DACB,C,D To 1/2 LSB, VDD=3V To 1/2 LSB, VDD=3V To 1/2 LSB, VDD=3V To 1/2 LSB, VDD=3V To 1/2 LSB, VDD=3V SYMBOL CONDITIONS MIN TYP 0.8 0.5 1 20 75 10 75 40 120* MAX UNIT V/S V/S V/S S S S S S
To 1/2 LSB, VDD=3V
25
75*
S
5
Measured at -3dB point CLK=1MHz sq. wave measured at DACA-DACD A,B,C,D inputs (note 15) A,B,C,D inputs (note 16) A,B,C,D inputs note 17 note 17
100 -50 -60 -60 -40 20 100
KHz dB dB dB dB kHz kHz
Notes: 3. This is tested by design but is not production tested. 4. This is measured with no load (open circuit output), Vref = 1.25V, range = x2. 5. Integral Nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full-scale errors). 6. Differential Nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 8. Zero scale error temperature coefficient is given by: ZCETC = (ZCE(Tmax) - ZCE(Tmin))/V REF x 10 6 / (Tmax - Tmin) 9. Full-Scale error is the deviation from the ideal full-scale output (Vref - 1LSB) with an output load of 10k. 10. Full-Scale Temperature Coefficient is given by: 6 FSETC = (FSE(Tmax) - FSE(Tmin))/VREF x 10 / (Tmax - Tmin) 11. Zero-code Error Rejection Ratio (ZCE-RR) is measured by varying the VDD voltage, from 4.75 to 5.25 V d.c., and measuring the proportion of this signal imposed on the zero-code output voltage.
7.
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WM5621L
Electrical Characteristics (continued)
12. Full Scale Error Rejection Ratio (FSE-RR) is measured by varying the VDD voltage, from 4.75 to 5.25 V d.c., and measuring the proportion of this signal imposed on the full-scale output voltage. 13. Linearity is only specified for DAC codes 1 through 255. 14. The ACT bit is latched on falling edge of EN. 15. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1Vdc + 1 Vpp at 10kHz. 16. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex with Vref input = 1Vdc + 1 Vpp at 10kHz. 17. Reference bandwidth is the -3dB bandwidth with an ideal input at Vref = 1.25 Vdc + 2 Vpp and with a digital input code of full-scale (range set to x1 and Vdd = 5V)
Typical Performance Characteristics
Typical DNL, INL and TUE at VDD = 5 V
Vd d = 5 .0 V, Vre f = 2 .5 V , R ang e = x1 @ 2 5' C
Differential Nonlinearity
o
Vdd = 5 .0V, Vre f = 2. 5V, Ra ng e = x1 @ 25 'C
Integral Nonlinearity
I ntegral Non Li neari ty
VDD = 5.0, VREF = 2.5V, Range = x1 at 25 C
0.2 0.15 0.1
VDD = 5.0, VREF = 2.5V, Range = x1 at 25 C
o
0.2 0.15
Error (LSBs)
Error (LSBs)
Err o r (lsb s)
0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 32 64 96 128
Co de Error (lsbs)
0.05 0 -0.05 -0.1 -0.15 -0.2
160
192
224
256
0
32
64
96
128
Co d e
160
192
224
256
Input Code
Input Code
Total Unadjusted Error
Vdd = 5.0 V, Vref = 2.5 V, Rang e = x 1 @ 25 'C
Differential Nonlinearity
o
Vdd = 5 .0V, Vre f = 2 .0V, Ran ge = x2 @ 25 'C
Total Unad justed Er ror VDD = 5.0, VREF = 2.5V, Range = x1 at 25 C
VDD = 5.0, VREF = Differenti al Non Li neari ty = x2 at 25 C 2.0V, Range
o
0.2 0.15
0.2 0.15
Error (LSBs)
0.1 0.05
Error (lsbs)
Error (LSBs)
Error (lsbs)
0.1 0.05 0 -0.05 -0.1 -0.15 -0.2
0 -0.05 -0.1 -0.15 -0.2 0 32 64 96 128
Cod e
160
192
224
256
0
32
64
96
128
Co d e
160
192
224
256
Input Code
Input Code
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WM5621L
Typical Performance Characteristics
Integral Nonlinearity
Vdd = 5 .0V, Vre f = 2 .0V, Ran ge = x2 @ 25'C
(continued) Total Unadjusted Error
VDD = 5.0, VREF = 2.0V, Range = x2 at 25 C
In teg ral Non Lin earity
o
Vdd = 5 .0V, Vre f = 2 .0V, Ran ge = x2 @ 25 'C
VDD = 5.0, VREF = 2.0V, Range = x2 at 25 C
To tal Un adju ste d E rror
o
0.2 0.15
0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 32 64 96 128
Co de
Error (LSBs)
0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 160 192 224 256
Error (LSBs)
Error (lsbs)
Error (lsbs)
0
32
64
96
128
Co d e
160
192
224
256
Input Code
Input Code
Typical DNL, INL and TUE at VDD = 3 V Differential Nonlinearity
Vdd = 3.0 V, Vref = 1.2 5V, Ran ge = x2 @ 25'C
Integral Nonlinearity
o
Vdd = 3.0V, Vref = 1.25V, Range =x2 @ 25'C I ntegral Non Li neari ty
Differen tial Non Lin earity
0.2 0.15
VDD = 3.0, VREF = 1.25V, Range = x2 at 25 C
0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 32 64 96 128
Cod e
VDD = 3.0, VREF = 1.25V, Range = x2 at 25 C
o
Error (LSBs)
0.1
Error (LSBs)
160 192 224 256
0 -0.05 -0.1 -0.15 -0.2
Error (lsbs)
0.05
Error (lsbs)
0
32
64
96
128
160
192
224
256
Input Code
Code Input Code
Total Unadjusted Error
Vdd = 3. 0V, Vre f = 1. 25 V, Ra ng e = x 2 @ 25 'C
VDD = 3.0, VREF = 1.25V, Range = x2 at 25 C
To tal Un adju sted E rror
o
0.2 0.15
Error (lsbs)
5
Error (LSBs)
0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 32 64 96 128
Co d e
160
192
224
256
Input Code
Output Source Current vs Output Voltage
VDD = 5.0, VREF = 2V, Range = 2x, Input Code = 255, Temperature = 25 C
o
Supply Current v Temperature
Supply Current vs Temperature
8 7 6
IOUT (mA)
Vdd = 5V, Vref = 2.0V, Range = 2x Input Code = 255, Temperature = 25'C
1.15 1.1 1.05
IDD (mA) IDD (mA)
Vdd = = 5.0, VREF = 2V, VDD 5V, Vref = 2.0V Range = 2x, Input Code = 255
Range = 2x, Input Code = 255
5
Iout (mA)
1 0.95 0.9 0.85 0.8 -30 -15
Vdd = 3V, = = 1.25V VDD =3.0, VREFVref1.25V, Range Range = 2x, Input Code 255 = 2x, Input Code = = 255
4 3 2 1 0 0 1 2
Vo ut VOUT (V) (V)
3
4
5
0
15
30
45
60
75
90
Tem p erature ('C) Temperature (oC)
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WM5621L
Typical Performance Characteristics (continued)
Large Signal Frequency Response
La rge Signal Fre que ncy Re sponse
Small Signal Frequency Response
Sm all Signa l Fre que nc y Re spons e
5 0 Relative Gain (dB) Relative Gain (dB)
Relative Gain (dB)
-5 -10 -15 -20 -25 1000
Vdd = 5V, Vref = 1.25V + 2V1.25V + 2Vpp, VDD = 5.0, VREF = pp Range = 1x, Input Code = 255 Range = 25'C Temperature = 1x, Input Code = 255 o
Temperature = 25 C
5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 1
Relative Gain (dB)
VDD= = 5V, VREF+= 2V + 1Vpp, Vdd 5V, Vref = 2V 1V pp Range = = Input Code = 255 Range 1x,1x, Input Code = 255 o Temperature = 25'C Temperature = 25 C
10000 100000 Frequency (KHz) Frequency (KHz)
1000000
10
100 Frequency (KHz) Frequency (KHz)
1000
10000
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WM5621L
Input and Output Circuits
Pin Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name GND REFA REFB REFC REFD DATA CLK EN DACD DACC DACB DACA HWACT VDD Type Supply Analogue input Analogue input Analogue input Analogue input Digital input Digital input Digital input Analogue output Analogue output Analogue output Analogue output Digital input Supply Function Ground return and reference terminal Reference voltage input to DACA Reference voltage input to DACB Reference voltage input to DACC Reference voltage input to DACD Serial interface data Serial interface clock, negative edge sensitive Input Enable DAC D output DAC C output DAC B output DAC A output Hardware activate Positive supply voltage
5
Timing Waveforms
Figure 1: Detailed timing of serial interface
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Figure 2: Serial write in double buffered mode. Registers are latched on falling edge of EN. Preceding ZEROs on DATA are ignored.
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Figure 3: Multiple DAC updates at the same time are possible by holding EN high over multiple serial words. All DACs are updated on the falling edge of EN.
Figure 4: In single buffered mode, synchronisation can be regained by clocking in at least 12 ZEROs. Registers are updated on the twelfth falling edge of CLK after a Start Bit has been detected.
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WM5621L
Functional Description
DAC operation Each of WM5621L's four digital to analogue converters (DACs) are implemented using a single resistor string with 256 taps corresponding to each of the input 8-bit codes. One end of a resistor string is connected to the GND pin and the other end is driven from the output of a reference input buffer. The use of a resistor string guarantees monotonicity of the DAC's output voltage. Linearity depends upon the matching of the resistor string's individual elements and the performance of the output buffer. The reference input buffers present a high impedance to reference sources. Each DAC has a voltage output amplifier which is programmable for gains of x1 or x2 through the serial interface. The DAC output amplifiers feature rail to rail output stages, allowing outputs over the full supply voltage range to be achieved with a x2 gain setting and a VDD/2 reference voltage input. Used in this way a slight degradation in linearity will occur as the output voltage approaches VDD. Control of the WM5621L is effected through a serial interface using three dedicated pins, CLK, DATA and EN. A fourth pin (HWACT) is used to control the power-down controls to each of the 4 DACs. Serial Interface The serial interface uses the CLK pin to clock in data words presented serially on the DATA pin. The data words are 12 bits long and are written to either a control register or to one of the four DAC registers. When the EN pin is held low the serial interface is held in reset. Figure 1 shows the format of the 12-bit data word transfer into the WM5621L. DATA is clocked on the falling edge of CLK. Every data word must start with a high start bit (preceeding zeros are ignored). The second bit is the register select bit which selects a write into either the control register or one of the DAC registers. Table 1 shows all valid write sequences. The serial interface can operate in one of two ways, controlled by the setting of the MODE bit in the control register. The MODE bit defaults to 0 on power up which sets the device to work in a double buffered mode. When MODE is set to 1, the device operates in a single buffered mode, which can be controlled through only two pins (DATA and CLK, EN held high). Double Buffered Mode In normal operation the EN signal is used to control the latching of data. All DAC registers and all bits of the control word (other than MODE) are double buffered, with the second buffer only being enabled when the EN pin is taken low. In this way it is possible to update any number of DAC inputs at once by writing a 12-bit word to update each DAC register, with EN held high for all writes. When EN is pulled low at the end of the last write, all DAC inputs are latched at the same time. Figure 3 shows DACs A and B being written to in this way. This mode also allows multiple devices to be share DATA and CLK lines by having only separate EN lines. Single Buffered Mode If the device is to be operated in single buffered mode, the EN pin should be tied high, and the interface is always active. The first write to the device after power-on should be a write to the control register to set the MODE bit high. The double buffered action is not possible as all words are latched across on the twelfth falling edge of CLK. Loss of synchronisation may occur if glitches are present on the CLK and DATA inputs, a condition which may occur at power-on. If this has happened it is possible to regain synchronisation by clocking in at least 12 zeros (see Figure 4). It is not possible to reset the MODE bit from 1 to 0. Operation of the device after any attempt to do this is undefined. DAC Registers Each DAC register holds an 8-bit unsigned byte to represent the DAC code. Table 1 indicates how these bytes are clocked into the DAC registers, with D7 being the most significant bit of the byte. These registers are reset to 0 at power-on.
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WM5621L
Functional Description (continued)
Control Word Start Bit 1 Register 0 Select 3 MODE 4 RNGA 5 RNGB 6 RNGC 7 RNGD 8 SIA 9 SIB 10 SIC 11 SID 12 ACT Table 1 Bit DACA Write 1 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 DACB Write 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 DACC Write 1 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0 DACD Write 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Bit Power-up state Function MODE 0 Control serial interface RNG A 1 DACA range select (0 = x1, 1 = x2) RNG B 1 DACB range select (0 = x1, 1 = x2) RNG C 1 DACC range select (0 = x1, 1 = x2) RNG D 1 DACD range select (0 = x1, 1 = x2) SIA 0 DACA shutdown inhibit SIB 0 DACB shutdown inhibit SIC 0 DACC shutdown inhibit SID 0 DACD shutdown inhibit ACT 0 Software shutdown control Table 2
SIA 0 0 0 0 1 1 1 1 Table 3
ACT 0 0 1 1 0 0 1 1
HWACT 0 1 0 1 0 1 0 1
DAC status shutdown shutdown shutdown active active active active active
Linearity, offset, and gain error using single end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However, because the most negative supply rail is GND, the output cannot drive to a negative voltage. So when the output offset voltage is negative, the output voltage remains at ZERO volts until the input code value produces a sufficient output voltage to overcome the inherent negative offset voltage, resulting in the transfer function shown in Figure 5. This negative offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive to a negative voltage.
Control Register The control register contains 10 active bits. The MODE bit controls the operation of the serial interface as described above. The function of the control register bits, and their state on power-up, are shown in table 2. The shutdown state of each DAC is controlled through the shutdown inhibit bit for that channel (SIx), the ACT bit of the control register, and the HWACT pin. Table 3 shows the logical action of these three controlling bits for DAC A. It is possible, for example, to have any combination of DACs switched from shutdown to active by the HWACT pin, while the remaining DACs are held always active (achieve this by setting ACT=1, SIx=0 for the switching DACs, and SIx=1 for the always active DACs).
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WM5621L
Functional Description (continued)
For a DAC, linearity is measured between ZERO input code ( all inputs 0 ) and full scale code ( all inputs 1 ) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity in the unipolar mode is measured between full scale code and the lowest code which produces a positive output voltage. The code is calculated from the maximum specification for the negative offset.
Figure 5: Effect of negative offset (single supply)
5
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WM5621L
Package Descriptions
Plastic Small-Outline Package D - 8 pins shown
4.00 3.80 8
A 5
6.20 5.80
1 1.75 1.35
4 0.50 0.25 0.19 x 45O NOM 0.25
0.51 0.25 0.10 0.33 Pin spacing 1.27 B.S.C. 0O to 8O 1.27 0.40
Dimension 'A' Variations N 8 14 16 Min 4.80 8.55 9.80 Max 5.00 8.75 10.00
Notes: A. Dimensions in millimeters. B. Complies with Jedec standard MS-012. C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion. E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall not exceed 0.25mm.
Rev. 1 November 96
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WM5621L
Package Descriptions
Dual-In-Line Package
N or P
N
0.325 0.290 0.015 Min.
1
N/2
A 0.070 Max.
0.280 0.240
0.210 Max. 105O 90O 0.014 0.008 0.150 0.115 0.005 Min. Pin spacing 0.100 B.S.C. 0.045 0.030 0.022 Seating plane
Dimension 'A' Variations
0.014
5
N 8 14 16 20
Min 0.355 0.735 0.735 0.940
Max 0.400 0.775 0.775 0.975
Notes: A. Dimensions are in inches B. Falls within JEDEC MS-001( 20 pin package is shorter than MS-001) C. N is the maximum number of terminals D. All end pins are partial width pins as shown, except the 14 pin package which is full width.
Rev. 1 November 96
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